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? semiconductor components industries, llc, 2016 january, 2017 ? rev. 10 1 publication order number: mt9m021/d mt9m021, mt9m031 mt9m021/mt9m031 1/3\inch cmos digital image sensor description the mt9m021/mt9m031 from on semiconductor is a 1/3-inch cmos digital image sensor with an active-pixel array of 1280 (h) 960 (v). it includes sophisticated camera functions such as auto exposure control, windowing, scaling, row ski p mode, and both video and single frame modes. it is designed for low light performance and features a global shutter for accurate capture of moving scenes. it is programmable through a simple two-wire serial interface. the mt9m021/mt9m031 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including scanning and hd video. table 1. key performance parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280 (h) 960 (v) = 1.2 mp pixel size 3.75 m color filter array rgb bayer or monochrome shutter type global shutter input clock range 6?50 mhz output pixel clock (maximum) 74.25 mhz output serial parallel hispi (ibga package only) 12-bit frame rate full resolution 720p 45 fps 60 fps responsivity monochrome color 6.1 v/lux?sec 5.3 v/lux?sec snr max 38 db dynamic range 64 db supply voltage i/o digital analog hispi 1.8 or 2.8 v 1.8 v 2.8 v 0.4 v power consumption < 400 mw operating temperature (ambient) ?30 c to + 70 c package options 9 9 mm 63-pin ibga 10 10 mm 48-pin ilcc www.onsemi.com f eatures ? superior low-light performance ? hd video (720p60) ? global shutter ? video/single frame mode ? flexible row-skip modes ? on-chip ae and statistics engine ? parallel and serial output ? support for external led or flash ? auto black level calibration ? context switching a pplications ? scene processing ? scanning and machine vision ? 720p60 video applications see detailed ordering and shipping information on page 2 o f this data sheet. ordering information ibga63 9 9 case 503aq ilcc48 10 10 case 847aj
mt9m021, mt9m031 www.onsemi.com 2 ordering information table 2. available part numbers part number product description orderable product attribute description mt9m021ia3xtc?dpbr1 1.2 mp 1/3 gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtc?drbr 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtm?dpbr1 1.2 mp 1/3 gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtm?drbr1 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtmz?dpbr 1.2 mp 1/3 gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtmz?drbr 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtmz?tpbr 1.2 mp 1/3 gs cis tape & reel with protective film, double side bbar glass mt9m031d00stmc24bc1?200 1 mp 1/6 soc die sales, 200 m thickness mt9m031i12stc?dpbr1 1 mp 1/6 soc dry pack with protective film, double side bbar glass mt9m031i12stc?drbr 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass mt9m031i12stm?dpbr 1.2 mp 1/3 gs cis dry pack with protective film, double side bbar glass mt9m031i12stm?drbr1 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass mt9m031i12stmz?drbr 1.2 mp 1/3 gs cis dry pack without protective film, double side bbar glass see the on semiconductor device nomenclature document ( tnd310/d ) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com . general description the on semiconductor mt9m021/mt9m031 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. the default mode output is a full-resolution image at 45 frames per second (fps). it outputs 12-bit raw data, using either the parallel or serial (hispi) output ports. the device may be operated in video (master) mode or in frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock. a dedicated flash pin can be programmed to control external led or flash exposure illumination. the mt9m021/mt9m031 includes additional features to allow application-specific tuning: windowing, adjustable auto-exposure control, auto black level correction, on-board temperature sensor, and row skip and digital binning modes. the sensor is designed to operate in a wide temperature range (?30 c to +70 c). functional overview the mt9m021/mt9m031 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. it uses an on-chip, phase-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock ru nning between 6 and 50 mhz. the maximum output pixel rate is 74.25 mp/s, corresponding to a clock rate of 74.25 mhz. f igure 1 shows a block diagram of the sensor. figure 1. block diagram control registers analog processing and a/d conversion active pixel sensor (aps) array pixel data path (signal processing) timing and control (sequencer) auto exposure and stats engine temperature sensor otpm memory pll external clock serial output parallel output flash trigger two-wire serial interface power
mt9m021, mt9m031 www.onsemi.com 3 user interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. the core of the sensor is a 1.2 mp active-pixel sensor array. the mt9m021/mt9m031 features global shutter technology for accurate capture of moving images. the exposure of the entire array is controlled by programming the integration time by register setting. all rows simultaneously integrate light prior to readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to-digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and line synchronization signals. features overview the mt9m021/mt9m031 global sensor shutter has a wide array of features to enhance functionality and to increase versatility. a summary of features follows. please refer to the mt9m021/mt9m031 developer guide for detailed feature descriptions, register settings, and tuning guidelines and recommendations. ? operating modes the mt9m021/mt9m031 works in master (video), trigger (single frame), or auto trigger modes. in master mode, the sensor generates the integration and readout timing. in trigger mode, it accepts an external trigger to start exposure, then generates the exposure and readout timing. the exposure time is programmed through the two-wire serial interface for both modes. note: trigger mode is not compatible with the hispi interface. ? window control configurable window size and blanking times allow a wide range of resolutions and frame rates. digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. ? context switching context switching may be used to rapidly switch between two sets of register values. refer to the mt9m021/mt9m031 developer guide for a complete set of context switchable registers. ? gain the mt9m021/mt9m031 global shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x. ? automatic exposure control the integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. refer to the mt9m021/mt9m031 developer guide for more details. ? hispi the mt9m021/mt9m031 global shutter image sensor supports two or three lanes of streaming-sp or packetized-sp protocols of on semiconductor?s high-speed serial pixel interface. ? pll an on chip pll provides reference clock flexibility and supports spread spectrum sources for improved emi performance. ? reset the mt9m021/mt9m031 may be reset by a register write, or by a dedicated input pin. ? output enable the mt9m021/mt9m031 output pins may be tri-stated using a dedicated output enable pin. ? temperature sensor ? black level correction ? row noise correction ? column correction ? test patterns several test patterns may be enabled for debug purposes. these include a solid color, color bar, fade to grey, and a walking 1s test pattern.
mt9m021, mt9m031 www.onsemi.com 4 typical configuration and pinout figure 2. serial 4-lane hispi interface 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the parallel interface output pads can be left unconnected if the serial output interface is used. 5. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the mt9m021/mt9m031 demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is minimized. 7. although 4 serial lanes are shown, the mt9m021/mt9m031 supports only 2- or 3-lane hispi. notes: flash slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n v dd _pll v dd _io v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd s data s clk extclk 1.5 k 2 1.5 k 2, 3 oe_bar reset_bar test to controller from controller master clock (6?50 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground standby v dd _slvs hispi power 1 v dd _pll pll power 1 slvs3_p slvs3_n slvsc_p slvsc_n v dd v dd _slvs 7 7
mt9m021, mt9m031 www.onsemi.com 5 figure 3. parallel pixel data interface 1. all power supplies must be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5 k , but a greater value may be used for slower two-wire speed. 3. this pull-up resistor is not required if the controller drives a valid logic level on s clk at all times. 4. the serial interface output pads can be left unconnected if the parallel output interface is used. 5. on semiconductor recommends that 0.1 f and 10 f decoupling capacitors for each power supply are mounted as close as possible to the pad. actual values and results may vary depending on the layout and design considerations. refer to the mt9m021/mt9m031 demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes i s minimized. notes: frame_valid line_valid pixclk flash v dd _io v dd v aa v aa _pix a gnd d gnd v aa _pix v aa v dd _io v dd extclk s data s clk 1.5 k 2 1.5 k 2, 3 trigger oe_bar reset_bar test to controller from controller master clock (6?50 mhz) digital i/o power 1 digital core power 1 analog power 1 analog power 1 analog ground digital ground d out [11:0] standby pll power 1 v dd _pll v dd _pll
mt9m021, mt9m031 www.onsemi.com 6 figure 4. 9 9 mm 63-ball ibga package top view (ball down) a b c d e f g h 12345678 v dd _pll extclk s addr line_ valid d out 8 d out 4 d out 0 slvscn v dd _slvs s clk frame_ valid d out 9 d out 5 d out 1 slvs0n slvscp slvs3n s data pixclk d out 10 d out 6 d out 2 slvs0p slvs2n slvs3p d gnd flash d out 11 d out 7 d out 3 slvs1n slvs2p d gnd d gnd d gnd d gnd d gnd d gnd slvs1p v dd v dd v dd v dd _io v dd _io v dd _io v dd _io v dd v aa a gnd v aa _pix reserved test trigger v dd _io v dd v aa a gnd v aa _pix reserved reserved oe_bar reset_ bar standby table 3. pin descriptions ? 63-ball ibga package name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n slvs0_p a3 output hispi serial data, lane 0, differential p slvs1_n a4 output hispi serial data, lane 1, differential n slvs1_p a5 output hispi serial data, lane 1, differential p standby a8 input standby-mode enable pin (active high) v dd _pll b1 power pll power slvsc_n b2 output hispi serial ddr clock differential n
mt9m021, mt9m031 www.onsemi.com 7 table 3. pin descriptions ? 63-ball ibga package (continued) name description type ibga pin slvsc_p b3 output hispi serial ddr clock differential p slvs2_n b4 output hispi serial data, lane 2, differential n slvs2_p b5 output hispi serial data, lane 2, differential p v aa b7, b8 power analog power extclk c1 input external input clock v dd _slvs c2 power hispi power slvs3_n c3 output hispi serial data, lane 3, differential n slvs3_p c4 output hispi serial data, lane 3, differential p d gnd c5, d4, d5, e5, f5, g5, h5 power digital gnd v dd a6, a7, b6, c6, d6 power digital power a gnd c7, c8 power analog gnd s addr d1 input two-wire serial address select s clk d2 input two-wire serial clock input s data d3 i/o two-wire serial data i/o v aa _pix d7, d8 power pixel power line_valid e1 output asserted when d out line data is valid frame_valid e2 output asserted when d out frame data is valid pixclk e3 output pixel clock out. d out is valid on rising edge of this clock flash e4 output control signal to drive external light sources v dd _io e6, f6, g6, h6, h7 power i/o supply power d out 8 f1 output parallel pixel data output d out 9 f2 output parallel pixel data output d out 10 f3 output parallel pixel data output d out 11 f4 output parallel pixel data output (msb) test f7 input manufacturing test enable pin (connect to d gnd ) d out 4 g1 output parallel pixel data output d out 5 g2 output parallel pixel data output d out 6 g3 output parallel pixel data output d out 7 g4 output parallel pixel data output trigger g7 input exposure synchronization input oe_bar g8 input output enable (active low) d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output d out 2 h3 output parallel pixel data output d out 3 h4 output parallel pixel data output reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default reserved e7, e8, f8 n/a reserved (do not connect)
mt9m021, mt9m031 www.onsemi.com 8 figure 5. 10 10 mm 48-pin ilcc package, parallel output 42 nc 7 41 nc 8 40 v aa 9 39 a gnd 10 38 v aa _pix 11 37 v aa _pix 12 36 v aa 13 35 a gnd 14 34 v aa 15 33 reserved 16 32 reserved 17 v dd _io 31 reserved 18 d out 7 d out 8 d out 9 d out 10 d out 11 v dd _io pixclk v dd s clk s data reset_bar v dd 6 d gnd 19 nc 5 extclk 20 nc 4 v dd _pll 21 standby 3 d out 6 22 oe_bar 2 d out 5 23 s addr 1 d out 4 24 test 48 d out 3 25 flash 47 d out 2 26 trigger 46 d out 1 27 frame_valid 45 d out 0 28 line_valid 44 d gnd 29 d gnd 43 nc 30 table 4. pin descriptions ? 48-pin ilcc package, parallel pin number name type description 1 d out 4 output parallel pixel data output 2 d out 5 output parallel pixel data output 3 d out 6 output parallel pixel data output 4 v dd _pll power pll power 5 extclk input external input clock 6 d gnd power digital ground 7 d out 7 output parallel pixel data output 8 d out 8 output parallel pixel data output 9 d out 9 output parallel pixel data output
mt9m021, mt9m031 www.onsemi.com 9 table 4. pin descriptions ? 48-pin ilcc package, parallel (continued) pin number description type name 10 d out 10 output parallel pixel data output 11 d out 11 output parallel pixel data output (msb) 12 v dd _ io power i/o supply power 13 pixclk output pixel clock out. d out is valid on rising edge of this clock 14 v dd power digital power 15 s clk input two-wire serial clock input 16 s data i/o two-wire serial data i/o 17 reset_bar input asynchronous reset (active low). all settings are restored to factory default 18 v dd _ io power i/o supply power 19 v dd power digital power 20 nc no connection 21 nc no connection 22 standby input standby-mode enable pin (active high) 23 oe_bar input output enable (active low) 24 s addr input two-wire serial address select 25 test input manufacturing test enable pin (connect to d gnd ) 26 flash output flash output control 27 trigger input exposure synchronization input 28 frame_valid output asserted when d out frame data is valid 29 line_valid output asserted when d out line data is valid 30 d gnd power digital ground 31 reserved n/a reserved (do not connect) 32 reserved n/a reserved (do not connect) 33 reserved n/a reserved (do not connect) 34 v aa power analog power 35 a gnd power analog ground 36 v aa power analog power 37 v aa _ pix power pixel power 38 v aa _ pix power pixel power 39 a gnd power analog ground 40 v aa power analog power 41 nc no connection 42 nc no connection 43 nc no connection 44 d gnd power digital ground 45 d out 0 output parallel pixel data output (lsb) 46 d out 1 output parallel pixel data output 47 d out 2 output parallel pixel data output 48 d out 3 output parallel pixel data output
mt9m021, mt9m031 www.onsemi.com 10 electrical specifications unless otherwise stated, the following specifications apply to the following conditions: v dd = 1.8 v ?0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8 v 0.3 v; v dd _slvs = 0.4 v ?0.1/+0.2; t a = ?30 c to +70 c; output load = 10 pf; pixclk frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 6 and table 5. figure 6. two-wire serial bus timing parameters s data s clk s sr p s t f t r t f t r t su;dat t hd;sta t su;sto t su;sta t buf t hd;dat t high t low t hd;sta note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 5. two-wire serial bus characteristics (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; t a = 25 c) parameter symbol standard mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition t hd;sta 4.0 ? 0.6 ? s low period of the s clk clock t low 4.7 ? 1.3 ? s high period of the s clk clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition t su;sta 4.7 ? 0.6 ? s data hold time t hd;dat 0 (note 4) 3.45 (note 5) 0 (note 6) 0.9 (note 5) s data set-up time t su;dat 250 ? 100 (note 6) ? ns rise time of both s data and s clk signals t r ? 1000 20 + 0.1cb (note 7) 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1cb (note 7) 300 ns set-up time for stop condition t su;sto 4.0 ? 0.6 ? s bus free time between a stop and start condition t buf 4.7 ? 1.3 ? s capacitive load for each bus line cb ? 400 ? 400 pf serial interface input pin capacitance cin_si ? 3.3 ? 3.3 pf
mt9m021, mt9m031 www.onsemi.com 11 table 5. two-wire serial bus characteristics (continued) (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; t a = 25 c) parameter unit fast-mode standard mode symbol parameter unit max min max min symbol s data max load capacitance cload_sd ? 30 ? 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd _io and v ilmax = 0.1 v dd _io levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. i/o timing by default, the mt9m021/mt9m031 launches pixel data, fv and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the rising edge of pixclk. the launch edge of pixclk can be configured in register r0x3028. see figure 7 and table 6 for i/o timing (ac) characteristics. figure 7. i/o timing diagram extclk pixclk data[11:0] line_valid/ frame_valid pxl_0 pxl_1 pxl_2 pxl_n t pf l t pl l t fp t rp t f t r 90% 90% 90% 90% 10% 10% 10% 10% t extclk t pd t plh t pfh frame_valid leads line_valid by 6 pixclks frame_valid trails line_valid by 6 pixclks
mt9m021, mt9m031 www.onsemi.com 12 table 6. i/o timing characteristics, parallel output (1.8 v v dd _io) (note 1) symbol definition condition min typ max unit f extclk input clock frequency 6 ? 50 mhz t extclk input clock period 20 ? 166 ns t r input clock rise time pll enabled ? 3 4 ns t f input clock fall time pll enabled ? 3 4 ns t rp pixclk rise time slew setting = 4 (default) 2.3 ? 4.6 ns t fp pixclk fall time slew setting = 4 (default) 3 ? 4.4 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency (note 2) nominal voltages, pll enabled 6 ? 74.25 mhz t pd pixclk to data valid nominal voltages, pll enabled ?3 2.3 4.5 ns t pfh pixclk to fv high nominal voltages, pll enabled ?3 1.5 4.5 ns t plh pixclk to lv high nominal voltages, pll enabled ?3 2.3 4.5 ns t pfl pixclk to fv low nominal voltages, pll enabled ?3 1.5 4.5 ns t pll pixclk to lv low nominal voltages, pll enabled ?3 2 4.5 ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf. 2. jitter from pixclk is already taken into account in the data for all of the output parameters. table 7. i/o timing characteristics, parallel output (2.8 v v dd _io) (note 1) symbol definition condition min typ max unit f extclk input clock frequency 6 ? 50 mhz t extclk input clock period 20 ? 166 ns t r input clock rise time pll enabled ? 3 4 ns t f input clock fall time pll enabled ? 3 4 ns t rp pixclk rise time slew setting = 4 (default) 2.3 ? 4.6 ns t fp pixclk fall time slew setting = 4 (default) 3 ? 4.4 ns pixclk duty cycle 40 50 60 % f pixclk pixclk frequency (note 2) nominal voltages, pll enabled 6 ? 74.25 mhz t pd pixclk to data valid nominal voltages, pll enabled ?3 2.3 4 ns t pfh pixclk to fv high nominal voltages, pll enabled ?3 1.5 4 ns t plh pixclk to lv high nominal voltages, pll enabled ?3 2.3 4 ns t pfl pixclk to fv low nominal voltages, pll enabled ?3 1.5 4 ns t pll pixclk to lv low nominal voltages, pll enabled ?3 2 4 ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf. 2. jitter from pixclk is already taken into account in the data for all of the output parameters. table 8. i/o rise slew rate (2.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 1.08 1.77 2.72 v/ns 6 default 0.77 1.26 1.94 v/ns 5 default 0.58 0.95 1.46 v/ns 4 default 0.44 0.70 1.08 v/ns 3 default 0.32 0.51 0.78 v/ns 2 default 0.23 0.37 0.56 v/ns 1 default 0.16 0.25 0.38 v/ns 0 default 0.10 0.15 0.22 v/ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf.
mt9m021, mt9m031 www.onsemi.com 13 table 9. i/o fall slew rate (2.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 1.00 1.62 2.41 v/ns 6 default 0.76 1.24 1.88 v/ns 5 default 0.60 0.98 1.50 v/ns 4 default 0.46 0.75 1.16 v/ns 3 default 0.35 0.56 0.86 v/ns 2 default 0.25 0.40 0.61 v/ns 1 default 0.17 0.27 0.41 v/ns 0 default 0.11 0.16 0.24 v/ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf. table 10. i/o rise slew rate (1.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 0.41 0.65 1.10 v/ns 6 default 0.30 0.47 0.79 v/ns 5 default 0.24 0.37 0.61 v/ns 4 default 0.19 0.28 0.46 v/ns 3 default 0.14 0.21 0.34 v/ns 2 default 0.10 0.15 0.24 v/ns 1 default 0.07 0.10 0.16 v/ns 0 default 0.04 0.06 0.10 v/ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf. table 11. i/o fall slew rate (1.8 v v dd _io) (note 1) parallel slew (r0x306e[15:13]) condition min typ max unit 7 default 0.42 0.68 1.11 v/ns 6 default 0.32 0.51 0.84 v/ns 5 default 0.26 0.41 0.67 v/ns 4 default 0.20 0.32 0.52 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.18 0.28 v/ns 1 default 0.08 0.12 0.19 v/ns 0 default 0.05 0.07 0.11 v/ns 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70 c ambient at 90% of v dd _io, and ?30 c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20 pf.
mt9m021, mt9m031 www.onsemi.com 14 dc electrical characteristics the dc electrical characteristics are shown in table 12, table 13, table 14, and table 15. table 12. dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _ io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _ pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _ io * 0.7 ? ? v v il input low voltage ? ? v dd _ io * 0.3 v i in input leakage current no pull-up resistor; v in = v dd _ io or d gnd 20 ? ? a v oh output high voltage v dd _ io ? 0.3 ? ? v v ol output low voltage v dd _ io = 2.8 v ? ? 0.4 v i oh output high current at specified v oh ?22 ? ? ma i ol output low current at specified v ol ? ? 22 ma caution: stresses greater than those listed in table 13 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. table 13. absolute maximum ratings symbol parameter minimum maximum unit v supply power supply voltage (all supplies) ?0.3 4.5 v i supply total power supply current ? 200 ma i gnd total ground current ? 200 ma v in dc input voltage ?0.3 v dd _ io + 0.3 v v out dc output voltage ?0.3 v dd _ io + 0.3 v t stg storage temperature (note 1) ?40 +85 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 14. operating current consumption for parallel output (v aa = v aa _pix = v dd _io = v dd _pll = 2.8 v; v dd = 1.8 v; pll enabled and pixclk = 74.25 mhz; t a = 25 c; c load = 10 pf) symbol parameter condition min typ max unit i dd digital operating current parallel, streaming, full resolution 45 fps ? 45 55 ma i dd _io i/o digital operating current parallel, streaming, full resolution 45 fps ? 50 (note 1) ? ma i aa analog operating current parallel, streaming, full resolution 45 fps ? 45 50 ma i aa _pix pixel supply current parallel, streaming, full resolution 45 fps ? 6 10 ma i dd _pll pll supply current parallel, streaming, full resolution 45 fps ? 6 8 ma 1. i dd _io operating current is specified with image at 1/2 saturation level.
mt9m021, mt9m031 www.onsemi.com 15 table 15. standby current consumption (analog ? v aa + v aa _pix + v dd _pll; digital ? v dd + v dd _io; t a = 25 c) definition condition min typ max unit hard standby (clock off, driven low) analog, 2.8 v ? 3 10 a digital, 1.8 v ? 8 75 a hard standby (clock on, extclk = 20 mhz) analog, 2.8 v ? 12 20 a digital, 1.8 v ? 0.87 1.3 ma soft standby (clock off, driven low) analog, 2.8 v ? 3 10 a digital, 1.8 v ? 8 75 a soft standby (clock on, extclk = 20 mhz) analog, 2.8 v ? 12 20 a digital, 1.8 v ? 0.87 1.3 ma hispi electrical specifications the on semiconductor mt9m021/mt9m031 sensor supports slvs mode only, and does not have a dll for timing adjustments. refer to the high-speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definitions, specifications, and timing information. the v dd _slvs supply in this data sheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the hispi transmitter electrical specifications are listed at 700 mhz. table 16. input voltage and current (hispi power supply 0.4 v) (measurement conditions: max freq. 700 mhz) symbol parameter min typ max unit i dd _slvs supply current (pwr hispi ) (driving 100 load) ? 10 15 ma v cmd hispi common mode voltage (driving 100 load) v dd _ slvs x 0.45 v dd _slvs/2 v dd _ slvs x 0.55 v |v od | hispi differential output voltage (driving 100 load) v dd _ slvs x 0.36 v dd _slvs/2 v dd _ slvs x 0.64 v v cm change in v cm between logic 1 and 0 ? ? 25 mv |v od | change in |v od | between logic 1 and 0 ? ? 25 mv nm v od noise margin ? ? 30 % | v cm | difference in v cm between any two channels ? ? 50 mv | v od | difference in v od between any two channels ? ? 100 mv v cm _ac common-mode ac voltage (pk) without v cm cap termination ? ? 50 mv v cm _ac common-mode ac voltage (pk) with v cm cap termination ? ? 30 mv v od _ac max overshoot peak |v od | ? ? 1.3 x |v od | v v diff_pkpk max overshoot v diff pk-pk ? ? 2.6 x |v od | v v eye eye height 1.4 x v od ? ? r o single-ended output impedance 35 50 70 r o output impedance mismatch ? ? 20 %
mt9m021, mt9m031 www.onsemi.com 16 figure 8. differential output voltage for clock and data pairs v diffmin v diffmax 0 v (diff) output signal is ?cp ? cn? or ?dp ? dn? table 17. rise and fall times (measurement conditions: hispi power supply 0.4 v, max freq. 700 mhz) symbol parameter min typ max unit 1/ui data rate 280 ? 700 mb/s txpre max setup time from transmitter (note 1) 0.3 ? ? ui txpost max hold time from transmitter 0.3 ? ? ui rise rise time (20?80%) ? 0.25 ui ? fall fall time (20?80%) 150 ps 0.25 ui ? pll_duty clock duty 45 50 55 % t pw bitrate period (note 1) 1.43 ? 3.57 ns t eye eye width (notes 1, 2) 0.3 ? ? ui t totaljit data total jitter (pk pk)@1e?9 (notes 1, 2) ? ? 0.2 ui t ckjit clock period jitter (rms) (note 2) ? ? 50 ps t cyjit clock cycle to cycle jitter (rms) (note 2) ? ? 100 ps t chskew clock to data skew (notes 1, 2) ?0.1 ? 0.1 ui t |physkew| phy-to-phy skew (notes 1, 5) ? ? 2.1 ui t diffskew mean differential skew (note 6) ?100 ? 100 ps 1. one ui is defined as the normalized mean time between one edge and the following edge of the clock. 2. taken from 0 v crossing point. 3. also defined with a maximum loading capacitance of 10 pf on any pin. the loading capacitance may also need to be less for higher bitr ates so the rise and fall times do not exceed the maximum 0.3 ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point.
mt9m021, mt9m031 www.onsemi.com 17 figure 9. eye diagram for clock and data signals data mask clock mask trigger/reference ui/2 ui/2 rise fall v diff max v diff txpre txpost 80% 20% v diff clkjitter figure 10. skew within the phy and output channels vcmd t cmpskew t chskew1phy
mt9m021, mt9m031 www.onsemi.com 18 power-on reset and standby timing power-up sequence the recommended power-up sequence for the mt9m021/mt9m031 is shown in figure 11 . the available power supplies (v dd _ io, v dd , v dd _ slvs , v dd _pll, v aa , v aa _ pix) must have the separation specified below. 1. turn on v dd _ pll power supply. 2. after 0?10 s, turn on v aa and v aa _ pix power supply. 3. after 0?10 s, turn on v dd _io power supply. 4. after the last power supply is stable, enable extclk. 5. assert reset_bar for at least 1 ms. 6. wait 150000 extclks (for internal initialization into software standby). 7. configure pll, output, and image settings to desired values. 8. wait 1 ms for the pll to lock. 9. set streaming mode (r0x301a[2] = 1). figure 11. power up extclk v dd _slvs (0.4) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _pll (2.8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t x hard reset internal initialization software standby pll lock streaming reset_bar table 18. power-up sequence symbol definition min typ max unit t 0 v dd _pll to v aa /v aa _pix 0 10 ? s t 1 v aa /v aa _pix to v dd _io 0 10 ? s t 2 v dd _io to v dd 0 10 ? s t 3 v dd to v dd _slvs 0 10 ? s t x xtal settle time ? 30 (note 1) ? ms t 4 hard reset 1 (note 2) ? ? ms t 5 internal initialization 150000 ? ? extclks t 6 pll lock time 1 ? ? ms 1. xtal settling time is component-dependent, usually taking about 10?100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc time must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after other supplies then the sensor may have functionality issues and will experience high current draw on this supply.
mt9m021, mt9m031 www.onsemi.com 19 power-down sequence the recommended power-down sequence for the mt9m021/mt9m031 is shown in figure 12 . the available power supplies (v dd _ io, v dd , v dd _ slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is active by setting standby r0x301a[2] = 0. 2. the soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io. 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 12. power down extclk v dd _pll (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) t 0 power down until next power up cycle t 1 t 2 t 3 t 4 v aa _pix v aa (2.8) table 19. power-down sequence symbol parameter min typ max unit t 0 v dd _slvs to v dd 0 ? ? s t 1 v dd to v dd _io 0 ? ? s t 2 v dd _io to v aa /v aa _pix 0 ? ? s t 3 v aa /v aa _pix to v dd _pll 0 ? ? s t 4 pwrdn until next pwrup time 100 ? ? ms 1. t 4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
mt9m021, mt9m031 www.onsemi.com 20 figure 13. quantum efficiency ? monochrome sensor 0 10 20 30 40 50 60 70 80 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) 1100 1000 900 700 600 500 400 800 figure 14. quantum efficiency ? color sensor 0 10 20 30 40 50 60 70 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) red green blue 400 500 600 700 800 1000 900
mt9m021, mt9m031 www.onsemi.com 21 package dimensions figure 15. 63-ball ibga package outline drawing (case 503aq) note: all dimensions in millimeters.
mt9m021, mt9m031 www.onsemi.com 22 package dimensions figure 16. 48-pin ilcc package outline drawing (case 847aj)
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